1. Field of the Invention
The invention relates to a solid-state imaging device including column-parallel analog-to-digital converters provided to outputs of a plurality of vertical signal lines and capable of moderating device accuracy and reducing a conversion time, to a method of driving the solid-state imaging device, and to a camera.
2. Description of the Related Art
As shown in FIG. 8, a known solid-state imaging device 400 including a column-parallel analog-to-digital converter generally uses a counter-ramp-type analog-to-digital converter using a single slope.
The operation of the analog-to-digital converter shown in FIG. 8 will be described with reference to a timing chart of FIG. 9. In a pixel array 410, a plurality of pixels 411-11 to 411-nm which convert external light into an electrical signal by photoelectric conversion are arranged in a matrix. A certain row in the pixel array 410 is selected by a vertical selection circuit 401. A pixel signal (hereinafter, referred to as a ‘pixel output signal’) is output from the pixels 411-11 to 411-nm in the selected row, that is, from vertical signal lines vsl1 to vslm extended in the column direction of the pixel array 410.
Each of the vertical signal lines vsl1 to vslm is connected to one of input terminals (positive terminal side or a non-inversion input terminal) of a comparator 431 provided at every column. A signal nslope output from an additionally provided digital-to-analog converter 420 to which an analog output (voltage) is supplied in accordance with a clock signal is connected to the other input terminal (negative terminal side or an inversion input terminal) of the comparator 431.
That is, if the pixel output signal output from one of the vertical signal lines vsl1 to vslm is smaller than the signal nslope output from the digital-to-analog converter 420, a signal ncompout output from the comparator 431 becomes a low level. Meanwhile, if the pixel output signal output from one of the vertical signal lines vsl1 to vslm is larger than the signal nslope output from the digital-to-analog converter 420, the signal ncompout output from the comparator 431 becomes a high level. The signal ncompout output from the comparator 431 is input to an n-bit counter 432 so as to increase or decrease a count value in accordance with a clock signal clk (FIG. 8 shows an example in which a value decreases one by one in accordance with the clock).
The count value becomes an initial value iinit by a reset signal rst. The count value is stopped to be increased or decreased when the signal ncompout output from the comparator 431 becomes a high level and n-bit counter 432 holds the count value at that time (value i in FIG. 9). The count value is output as an n-bit output data [n−1:0] of the n-bit counter 432. That is, the count value is composed and sequentially output with outputs from other counters provided at different columns.
Further, as shown in FIG. 10, another solid-state imaging device 500 including a column-parallel analog-to-digital converters 530-1 (to 530-m) isprovided. It is an example that so-called successive approximation analog-to-digital converter 530-1 (to 530-m) is used in the solid-state imaging device 500.
First, the structure of the column-parallel analog-to-digital converter 530-1 (to 530-m) shown in FIG. 10 will be described. Next, the operation of the analog-to-digital conversion will be described with reference to a timing chart of FIG. 11.
As the same as shown in FIG. 8, a vertical signal lines vsl1 (to vslm) is connected to a positive terminal side of a comparator 531.
A signal ncompout output from the comparator 531 is input to a latch-logic circuit 532. The latch-logic circuit 532 outputs a plurality of control signals of a plurality of switches 534-1 to 534-n and 535-1 to 535-n connected to polar plates of a plurality of capacitors C(533-1), C/2 (533-2), . . . , and C/2n (533-n) which have capacitances. The switches 534-1 to 534-n and 535-1 to 535-n connect the polar plates to a vref2 terminal or a ground. The other polar plates of the capacitors C(533-1), C/2(533-2), . . . , and C/2n (533-n) are connected to a negative terminal side vcomp of the comparator 531. Further, the negative terminal side vcomp of the comparator 531 and the vertical signal lines vsl1 to vslm are connected to the vref1 terminal through the switches 536 to 537 which use the reset signal rst as a control signal.
Next, the operation of the successive approximation analog-to-digital converter 530-1 (to 530-m) will be described.
When the reset signal rst becomes a high level, the negative terminal side vcomp of the comparator 531 and the vertical signal line vs1 have a voltage which is at the same level as the voltage vref1. Further, a voltage at polar plate opposite to the comparator 531 of all the capacitors C(533-1), C/2(533-2), . . . , and C/2n (533-n) is connected to the ground. Therefore, the reset operation is performed.
Next, when a signal is read out from the pixels 511-11 to 511-nm, a level of the vertical signal line vsl1 (to vslm) becomes a level of the voltage in accordance with the read out signal. At this time, when the clock signal clk is at a high level, the latch-logic circuit 532 outputs a control signal of the switch 534-1 such that the voltage vref2 is applied to the polar plate of the capacitor C(533-1) in the direction opposite to the comparator 531.
Therefore, the voltage of the negative terminal side vcomp of the comparator 531 becomes a voltage vref1+vref2 so as to perform a comparison operation of an (n−1)-th bit comparator 531. At this time, in the embodiment of FIG. 10, since a level of signal vsl is higher than a voltage level of the negative terminal side vcomp, the comparator 531 outputs a signal at a high level (time t6). When the clock signal clk is at a low level, the value of the clock signal clk is latched as data[n−1] (time t7).
Next, when the clock signal clk is at a high level (time t8), the latch-logic circuit 532 outputs a control signal of the switches 534-2 and 535-2 such that the voltage vref2 is applied to the polar plate of the capacitor C/2 (533-2) in the direction opposite to the comparator 531. Then, the voltage of the negative terminal side vcomp of the comparator 531 becomes a voltage vref1+vref2/2. Therefore, the comparison operation of an (n−2)-th bit comparator 531 is performed.
At this time, in the embodiment of FIG. 10, a voltage level of the negative terminal side vcomp is set to be higher than a level of the signal vsl and the control signals of the switches 534-2 and 535-2 are output from the latch-logic circuit 532. Therefore, the voltage of the negative terminal side vcomp becomes a voltage vref1+vref2/2. Therefore, a comparison operation of an (n−2)-th bit comparator 531 is performed.
At this time, in the embodiment of FIG. 10, since the voltage level of the vertical signal line vsl1 is lower than the voltage level of the negative terminal side vcomp, the comparator 531 outputs a signal at a low level. When the clock signal clk is at a low level, the value of the output signal is latched as data [n−2] (time t9). When the clock signal clk is at a high level, the polar plate of the capacitor C/2 in the direction opposite to the comparator 531 is connected to the ground.
Hereinafter, by repeating the same operation until the capacitor C/2n (533-n), a value of n-bit data data[n−1:0] is determined and sent through a data line. A similar technology is disclosed in JP-A-2002-34037.